1. Field of the Invention
This disclosure relates to non-volatile memory.
2. Description of the Related Art
Semiconductor memory has become more popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in personal navigation devices, cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. Electrical Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories.
Both EEPROM and flash memory utilize a floating gate that is positioned above and insulated from a channel region in a semiconductor substrate. The floating gate and channel regions are positioned between the source and drain regions. A control gate is provided over and insulated from the floating gate. The threshold voltage of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to permit conduction between its source and drain is controlled by the level of charge on the floating gate.
Some EEPROMs or flash memory devices have a configuration referred to as a NAND configuration in which memory cells are grouped as NAND strings with each NAND string associated with a bit line. When programming an EEPROM or flash memory device, such as a NAND flash memory device, typically a program voltage is applied to the control gate and the bit line is grounded. Electrons from the channel are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory cell is raised so that the memory cell is in a programmed state. More information about programming can be found in U.S. Pat. No. 6,859,397, titled “Source Side Self Boosting Technique for Non-Volatile Memory;” U.S. Pat. No. 6,917,542, titled “Detecting Over Programmed Memory;” and U.S. Pat. No. 6,888,758, titled “Programming Non-Volatile Memory,” all three cited patents are incorporated herein by reference in their entirety.
In many cases, the program voltage is applied to the control gate as a series of pulses (referred to as programming pulses), with the magnitude of the pulses increasing with each pulse. Between programming pulses, a set of one or more verify operations are performed to determine whether the memory cell(s) being programmed have reached their target level. If a memory cell has reached its target level, programming stops for that memory cell. If a memory cell has not reached its target level, programming will continue for that memory cell.
In some implementations, the memory cells are erased prior to programming. Erasing can be performed on the entire memory array, on individual blocks, or another unit of cells. In one implementation, a group of memory cells is erased by raising p-wells of the memory cells to an erase voltage for a sufficient period of time. An erase pulse moves the threshold voltage of the memory cells towards (or beyond) an erase target level, which may be below 0 Volts. In some implementations, after applying the erase pulse, an erase verify operation is performed to determine whether the threshold voltages of the memory cells have at least reached the erase target level. The erase pulse and erase verify are repeated with each loop using a higher amplitude erase pulse until the erase verify passes.
After erasing the memory cells, some memory cells may be over-erased. That is, the threshold voltage of some memory cells is pushed past the target level. For example, the threshold voltage is more negative than desired. Furthermore, the range of threshold voltages of the memory cells may be wider than desired, which can negatively impact the quality of later programming. To tighten the erase distribution and combat over-erasing, the memory cells may be “soft programmed,” which compacts the threshold voltage distribution by increasing the lowest threshold voltages of erased memory cells while not significantly increasing the highest threshold voltages of erased memory cells. Soft programming may be performed in a similar manner as the previously described programming, but uses programming pulses with lower voltage magnitudes than regular programming. In one implementation, the soft programming is performed in loops in which each successively higher amplitude soft program pulse is followed by a soft program verify operation.
The process of erasing the memory cells and verifying the erase has drawbacks including the amount of time taken and power consumed. In some implementations, each of the erase pulses biases up substantial portions of the memory device. Therefore, ramping up to the final erase voltage takes considerable time. For example, it may take hundreds of micro-seconds to ramp up to the final erase voltage. Furthermore, because this high voltage pulse is applied over a long duration, considerable power is consumed.
In some cases, the target level that needs to be verified by the erase verify or the soft programming verify is a negative value. In one implementation, negative threshold voltages are sensed by pre-discharging bit lines to ground and then applying a higher than zero voltage (e.g., 2.2V) to the common source line. This causes current to flow from the source to the bit lines causing the bit lines to charge up towards the source line voltage. Charging of the bit lines stops when the body effect turns off at least one of the memory cells in a NAND chain. Using this technique, negative threshold voltages approaching −Vdd multiplied by the body effect factor (e.g., 2.2×1.5 where 2.2V is the VDD and 1.5 is the body effect factor) can be measured. However, a single erase verify or soft program verify can take about 100 micro-seconds.
Another technique for sensing a negative threshold voltage in a memory cell is to apply a negative voltage to the control gates of the memory cells. However, generating and/or delivering the necessary negative voltages can be difficult. Moreover, the more negative the voltage to be generated the more difficult it is to generate the voltage. Delivering negative voltages to word lines can be very difficult as it may require more than one type (n-type vs. p-type) of transistor in the decoder. This can lead to very large and expensive world line decoders, or even decoders that cannot match the small pitch of the memory array.
One technique to increase performance is to use fewer erase pulses by using large erase voltage step sizes. For example, rather than stepping up the erase voltage pulse by 0.5 volts with each successive erase pulse, the erase voltage could be stepped by 1.0 volt. However, using large voltage step sizes may lead to over-erasing. In some implementation, using a step size of 1.0 volt could lead to over-erasing some of the memory cells by about 1.0 volt. In one implementation, the erase process is completed with a single very high voltage erase pulse. However, using a single very high magnitude erase pulse can lead to extreme over-erasing.
To correct the over-erasing when using a single erase pulse, a large number of soft programming pulses may be used. In one implementation, about 15-20 soft programming pulses and soft verify operations are used. As each soft programming verify may take about 100 micro-seconds, substantial time can be used during the soft programming.